欢迎访问ic37.com |
会员登录 免费注册
发布采购

5M160ZT100I5 参数 Datasheet PDF下载

5M160ZT100I5图片预览
型号: 5M160ZT100I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号5M160ZT100I5的Datasheet PDF文件第148页浏览型号5M160ZT100I5的Datasheet PDF文件第149页浏览型号5M160ZT100I5的Datasheet PDF文件第150页浏览型号5M160ZT100I5的Datasheet PDF文件第151页浏览型号5M160ZT100I5的Datasheet PDF文件第153页浏览型号5M160ZT100I5的Datasheet PDF文件第154页浏览型号5M160ZT100I5的Datasheet PDF文件第155页浏览型号5M160ZT100I5的Datasheet PDF文件第156页  
8–4  
Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices  
IEEE Std. 1149.1 Boundary-Scan Register  
Figure 8–3 shows how test data is serially shifted around the periphery of the IEEE  
Std. 1149.1 device.  
Figure 8–3. Boundary-Scan Register  
Each peripheral  
element is either an  
I/O pin, dedicated  
input pin, or  
Internal Logic  
dedicated  
configuration pin.  
TAP Controller  
TDI  
TMS  
TDO  
TCK  
Boundary-Scan Cells of a MAX V Device I/O Pin  
Except for the four JTAG pins and power pins, you can use all the pins of a MAX V  
device (including clock pins) as user I/O pins and have a BSC. The 3-bit BSC consists  
of a set of capture registers and a set of update registers. The capture registers can  
connect to internal device data through the OUTJand OEJsignals, while the update  
registers connect to external data through the PIN_OUTand PIN_OEsignals. The TAP  
controller internally generates the SHIFT CLOCK, and UPDATEglobal control signals for  
,
the IEEE Std. 1149.1 BST registers; a decode of the instruction register generates the  
MODEsignal. The data signal path for the boundary-scan register runs from the serial  
data in (SDI) signal to the serial data out (SDO) signal. The scan register begins at the  
TDIpin and ends at the TDOpin of the device.  
MAX V Device Handbook  
December 2010 Altera Corporation  
 复制成功!