Cyclone V Device Overview
CV-51001 | 2018.05.07
Figure 10.
Device Chip Overview for Cyclone V GX and GT Devices
The figure shows a Cyclone V FPGA with transceivers. Different Cyclone V devices may have a different
floorplans than the one shown here.
I/O, LVDS, and Memory Interface
Hard Memory Controller
Hard
PCS
Transceiver
PMA
Hard
PCS
Transceiver
PMA
Hard
PCS
Transceiver
PMA
Transceiver
Individual Channels
Core Logic Fabric and MLABs
M10K Internal Memory Blocks
Variable-Precision DSP Blocks
Hard Memory Controller
I/O, LVDS, and Memory Interface
PMA Features
To prevent core and I/O noise from coupling into the transceivers, the PMA block is
isolated from the rest of the chip—ensuring optimal signal integrity. For the
transceivers, you can use the channel PLL of an unused receiver PMA as an additional
transmit PLL.
Table 22.
PMA Features of the Transceivers in Cyclone V Devices
Features
Backplane support
PLL-based clock recovery
Capability
Driving capability up to 6.144 Gbps
Superior jitter tolerance
Programmable deserialization and word Flexible deserialization width and configurable word alignment pattern
alignment
Equalization and pre-emphasis
•
•
Up to 14.37 dB of pre-emphasis and up to 4.7 dB of equalization
No decision feedback equalizer (DFE)
Ring oscillator transmit PLLs
Input reference clock range
614 Mbps to 6.144 Gbps
20 MHz to 400 MHz
Transceiver dynamic reconfiguration
Allows the reconfiguration of a single channel without affecting the operation of
other channels
Cyclone V Device Overview
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ALTERA [ ALTERA CORPORATION ]
