Cyclone V Device Overview
CV-51001 | 2018.05.07
PCS Support
Data Rates
(Gbps)
Transmitter Data Path Feature
Receiver Data Path Feature
Serial ATA Gen1 and Gen2
1.5 and 3.0
•
Custom PHY IP core with preset
feature
•
Custom PHY IP core with preset
feature
•
Electrical idle
•
•
Signal detect
Wider spread of asynchronous
SSC
CPRI 4.1(16)
OBSAI RP3
0.6144 to 6.144
0.768 to 3.072
•
•
Dedicated deterministic latency
PHY IP core
•
•
Dedicated deterministic latency
PHY IP core
Transmitter (TX) manual bit-slip
mode
Receiver (RX) deterministic
latency state machine
V-by-One HS
Up to 3.75
Custom PHY IP core
•
•
Custom PHY IP core
Wider spread of asynchronous
SSC
DisplayPort 1.2(17)
1.62 and 2.7
SoC with HPS
Each SoC combines an FPGA fabric and an HPS in a single device. This combination
delivers the flexibility of programmable logic with the power and cost savings of hard
IP in these ways:
•
•
•
Reduces board space, system power, and bill of materials cost by eliminating a
discrete embedded processor
Allows you to differentiate the end product in both hardware and software, and to
support virtually any interface standard
Extends the product life and revenue through in-field hardware and software
updates
HPS Features
The HPS consists of a dual-core Arm Cortex-A9 MPCore processor, a rich set of
peripherals, and a shared multiport SDRAM memory controller, as shown in the
following figure.
(16)
(17)
High-voltage output mode (1000-BASE-CX) is not supported.
Pending characterization.
Cyclone V Device Overview
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ALTERA [ ALTERA CORPORATION ]
