Cyclone V Device Overview
CV-51001 | 2018.05.07
Figure 11.
HPS with Dual-Core Arm Cortex-A9 MPCore Processor
Configuration
Controller
Lightweight
HPS-to-FPGA
FPGA Fabric
HPS
FPGA-to-HPS HPS-to-FPGA
FPGA-to-HPS SDRAM
FPGA
Manager
Debug
Access Port
MPU Subsystem
ARM Cortex-A9 MPCore
ETR
(Trace)
CPU0
CPU1
ARM Cortex-A9
with NEON/FPU,
ARM Cortex-A9
with NEON/FPU,
Multiport
DDR SDRAM
Controller
with
SD/MMC
Controller
32 KB Instruction Cache, 32 KB Instruction Cache,
32 KB Data Cache, and 32 KB Data Cache, and
Memory Management Memory Management
Ethernet
MAC (2x)
Optional ECC
Unit
Unit
Level 3
Interconnect
USB
OTG (2x)
ACP
SCU
NAND Flash
Controller
Level 2 Cache (512 KB)
DMA
Controller
STM
64 KB
Boot ROM
64 KB
On-Chip RAM
Peripherals
(UART, Timer, I2 C, Watchdog Timer, GPIO, SPI, Clock Manager, Reset Manager, Scan Manager, System Manager, and Quad
SPI Flash Controller)
System Peripherals and Debug Access Port
Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC controller module
has an integrated DMA controller. For modules without an integrated DMA controller,
an additional DMA controller module provides up to eight channels of high-bandwidth
data transfers. Peripherals that communicate off-chip are multiplexed with other
peripherals at the HPS pin level. This allows you to choose which peripherals to
interface with other devices on your PCB.
The debug access port provides interfaces to industry standard JTAG debug probes
and supports Arm CoreSight debug and core traces to facilitate software development.
Cyclone V Device Overview
29
ALTERA [ ALTERA CORPORATION ]
