Cyclone V Device Overview
CV-51001 | 2018.05.07
M10K
RAM Bit (Kb)
MLAB
RAM Bit (Kb)
Member
Code
Total RAM Bit
Variant
Block
446
686
1,220
140
270
397
553
140
270
397
553
397
553
Block
679
1338
2748
221
370
768
994
221
370
768
994
768
994
(Kb)
4,884
7,696
13,917
1,538
2,460
4,450
6,151
1,538
2,460
4,450
6,151
4,450
6,151
Cyclone V GT
D5
D7
D9
A2
A4
A5
A6
C2
C4
C5
C6
D5
D6
4,460
6,860
12,200
1,400
2,700
3,970
5,530
1,400
2,700
3,970
5,530
3,970
5,530
424
836
1,717
138
231
480
621
138
231
480
621
480
621
Cyclone V SE
Cyclone V SX
Cyclone V ST
Embedded Memory Configurations
Table 19.
Supported Embedded Memory Block Configurations for Cyclone V Devices
This table lists the maximum configurations supported for the embedded memory blocks. The information is
applicable only to the single-port RAM and ROM modes.
Memory Block
MLAB
Depth (bits)
Programmable Width
x16, x18, or x20
x40 or x32
x20 or x16
x10 or x8
32
256
512
1K
M10K
2K
x5 or x4
4K
x2
8K
x1
Clock Networks and PLL Clock Sources
550 MHz Cyclone V devices have 16 global clock networks capable of up to operation.
The clock network architecture is based on Intel's global, quadrant, and peripheral
clock structure. This clock structure is supported by dedicated clock input pins and
fractional PLLs.
Note:
To reduce power consumption, the Intel Quartus Prime software identifies all unused
sections of the clock network and powers them down.
Cyclone V Device Overview
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