Cyclone V Device Overview
CV-51001 | 2018.05.07
Figure 8.
ALM for Cyclone V Devices
FPGA Device
Reg
Reg
1
2
3
4
5
6
7
Full
Adder
Adaptive
LUT
Reg
Reg
8
Full
Adder
You can configure up to 25% of the ALMs in the Cyclone V devices as distributed
memory using MLABs.
Related Information
Embedded Memory Capacity in Cyclone V Devices on page 21
Lists the embedded memory capacity for each device.
Variable-Precision DSP Block
Cyclone V devices feature a variable-precision DSP block that supports these features:
•
Configurable to support signal processing precisions ranging from 9 x 9, 18 x 18
and 27 x 27 bits natively
•
•
•
•
A 64-bit accumulator
A hard preadder that is available in both 18- and 27-bit modes
Cascaded output adders for efficient systolic finite impulse response (FIR) filters
Internal coefficient register banks, 8 deep, for each multiplier in 18- or 27-bit
mode
•
•
Fully independent multiplier operation
A second accumulator feedback register to accommodate complex multiply-
accumulate functions
•
•
Fully independent Efficient support for single-precision floating point arithmetic
The inferability of all modes by the Intel Quartus Prime design software
Cyclone V Device Overview
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