Cyclone V Device Overview
CV-51001 | 2018.05.07
Resource
Member Code
C2
C4
3
C5
3
C6
3
HPS PLL
3
3 Gbps Transceiver
6
6
9
9
(8)
FPGA GPIO
145
145
181
32
37
2
288
181
72
72
288
181
72
72
HPS I/O
181
LVDS
Transmitter
Receiver
32
37
(9)
(9)
PCIe Hard IP Block
2
2
2
FPGA Hard Memory Controller
HPS Hard Memory Controller
Arm Cortex-A9 MPCore Processor
1
1
1
1
1
1
1
1
Dual-core
Dual-core
Dual-core
Dual-core
Related Information
True LVDS Buffers in Devices, I/O Features in Cyclone V Devices
Provides the number of LVDS channels in each device package.
Package Plan
Table 13.
Package Plan for Cyclone V SX Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific
I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
Member Code
U672
F896
(23 mm)
(31 mm)
FPGA GPIO
145
HPS I/O
181
XCVR
FPGA GPIO
HPS I/O
—
XCVR
C2
C4
C5
C6
6
6
6
6
—
—
—
—
9
145
181
—
145
181
288
288
181
145
181
181
9
Cyclone V ST
This section provides the available options, maximum resource counts, and package
plan for the Cyclone V ST devices.
The information in this section is correct at the time of publication. For the latest
information and to get more details, refer to the Product Selector Guide.
(8)
(9)
The number of GPIOs does not include transceiver I/Os. In the Intel Quartus Prime software,
the number of user I/Os includes transceiver I/Os.
1 PCIe Hard IP Block in U672 package.
Cyclone V Device Overview
15
ALTERA [ ALTERA CORPORATION ]
