AV-51002
2017.02.10
1-47
PLL Specifications
Symbol
tCASC_OUTPJ_DC
tDRIFT
Parameter
Condition
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
Min
—
Typ
—
Max
175
17.5
10
Unit
ps (p-p)
Period jitter for dedicated clock output
in cascaded PLLs
(67)(71)
—
—
mUI (p-p)
%
Frequency drif afer PFDENAis disabled
—
—
for a duration of 100 µs
dKBIT
Bit number of Delta Sigma Modulator
(DSM)
—
8
24
32
bits
kVALUE
fRES
Numerator of fraction
—
128
8388608
5.96
2147483648
0.023
—
Resolution of VCO frequency
fINPFD = 100 MHz
390625
Hz
Related Information
Memory Output Clock Jitter Specifications on page 1-57
Provides more information about the external memory interface clock output jitter specifications.
(71)
e cascaded PLL specification is only applicable with the following conditions:
• Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
• Downstream PLL: Downstream PLL BW > 2 MHz
Arria V GX, GT, SX, and ST Device Datasheet
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