AV-51002
2017.02.10
1-45
PLL Specifications
Symbol
Parameter
Condition
–3 speed grade
–4 speed grade
–5 speed grade
–6 speed grade
—
Min
—
Typ
—
—
—
—
50
Max
Unit
670(63)
670(63)
622(63)
500(63)
55
MHz
MHz
MHz
MHz
%
—
Output frequency for external clock
output
fOUT_EXT
—
—
tOUTDUTY
tFCOMP
tDYCONFIGCLK
tLOCK
Duty cycle for external clock output
(when set to 50%)
45
External feedback clock compensation
time
—
—
—
—
—
—
—
—
—
10
100
1
ns
MHz
ms
Dynamic configuration clock for mgmt_
clkand scanclk
Time required to lock from end-of-
device configuration or deassertion of
areset
tDLOCK
Time required to lock dynamically
(afer switchover or reconfiguring any
non-post-scale counters/delays)
—
—
—
1
ms
Low
Medium
High(64)
—
—
—
—
—
10
0.3
1.5
4
—
—
—
50
—
MHz
MHz
MHz
ps
fCLBW
PLL closed-loop bandwidth
tPLL_PSERR
tARESET
Accuracy of PLL phase shif
—
—
Minimum pulse width on the areset
—
ns
signal
FREF ≥ 100 MHz
FREF < 100 MHz
—
—
—
—
0.15
750
UI (p-p)
ps (p-p)
(65)(66)
tINCCJ
Input clock cycle-to-cycle jitter
(64)
High bandwidth PLL settings are not supported in external feedback mode.
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
FREF is fIN/N, specification applies when N = 1.
(65)
(66)
Arria V GX, GT, SX, and ST Device Datasheet
Send Feedback
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
