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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
1-43  
Core Performance Specifications  
Protocol  
Sub-protocol  
SONET 155  
SONET 622  
SONET 2488  
GPON 155  
Data Rate (Mbps)  
155.52  
SONET  
622.08  
2,488.32  
155.52  
GPON 622  
622.08  
Gigabit-capable passive optical network (GPON)  
QSGMII  
GPON 1244  
GPON 2488  
QSGMII 5000  
1,244.16  
2,488.32  
5,000  
Core Performance Specifications  
Clock Tree Specifications  
Table 1-35: Clock Tree Specifications for Arria V Devices  
Performance  
–I5, –C5  
625  
Parameter  
–I3, –C4  
Unit  
–C6  
525  
350  
Global clock and Regional clock  
Peripheral clock  
625  
450  
MHz  
MHz  
400  
PLL Specifications  
Table 1-36: PLL Specifications for Arria V Devices  
is table lists the Arria V PLL block specifications. Arria V PLL block does not include HPS PLL.  
Arria V GX, GT, SX, and ST Device Datasheet  
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Altera Corporation  
 
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