AV-51002
2017.02.10
1-44
PLL Specifications
Symbol
Parameter
Condition
–3 speed grade
–4 speed grade
–5 speed grade
–6 speed grade
—
Min
5
Typ
—
—
—
—
—
Max
800(61)
800(61)
750(61)
625(61)
325
Unit
MHz
MHz
MHz
MHz
MHz
5
fIN
Input clock frequency
5
5
fINPFD
Integer input clock frequency to the
phase frequency detector (PFD)
5
fFINPFD
Fractional input clock frequency to the
PFD
—
50
—
160
MHz
–3 speed grade
–4 speed grade
–5 speed grade
–6 speed grade
—
600
600
600
600
40
—
—
—
—
—
1600
1600
1600
1300
60
MHz
MHz
MHz
MHz
%
PLL voltage-controlled oscillator
(VCO) operating range
(62)
fVCO
tEINDUTY
Input clock or external feedback clock
input duty cycle
–3 speed grade
–4 speed grade
–5 speed grade
–6 speed grade
—
—
—
—
—
—
—
—
500(63)
500(63)
500(63)
400(63)
MHz
MHz
MHz
MHz
Output frequency for internal global or
regional clock
fOUT
(61)
is specification is limited in the Quartus Prime sofꢂare by the I/O maximum frequency. e maximum I/O frequency is different for each I/O
standard.
(62)
(63)
e VCO frequency reported by the Quartus Prime sofꢂare takes into consideration the VCO post-scale counter Kvalue. ereꢃore, if the counter K
has a value of 2, the frequency reported can be lower than the fVCO specification.
is specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
Arria V GX, GT, SX, and ST Device Datasheet
Send Feedback
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
