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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
2-55  
OCT Calibration Block Specifications  
OCT Calibration Block Specifications  
Table 2-51: OCT Calibration Block Specifications for Arria V GZ Devices  
Symbol  
OCTUSRCLK  
TOCTCAL  
Description  
Min  
Typ  
Max  
20  
Unit  
MHz  
Cycles  
Cycles  
ns  
Clock required by the OCT calibration blocks  
Number of OCTUSRCLK clock cycles required for OCT RS/RT calibration  
Number of OCTUSRCLK clock cycles required for the OCT code to shif out  
1000  
32  
TOCTSHIFT  
TRS_RT  
Time required between the dyn_term_ctrland oesignal transitions in a  
bidirectional I/O buffer to dynamically switch between OCT RS and RT (See  
the figure below.)  
2.5  
Figure 2-6: Timing Diagram for oe and dyn_term_ctrl Signals  
Tristate  
Tristate  
RX  
oe  
TX  
RX  
dyn_term_ctrl  
T
T
RS_RT  
RS_RT  
Arria V GZ Device Datasheet  
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Altera Corporation  
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