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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
2-58  
DCLK-to-DATA[] Ratio (r) for FPP Configuration  
Table 2-55: DCLK-to-DATA[] Ratio for Arria V GZ Devices  
Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r times the data rate in bytes per second (Bps), or words per  
second (Wps). For example, in FPP ×16 when the DCLK-to-DATA[]ratio is 2, the DCLKfrequency must be 2 times the data rate in Wps. Arria V GZ  
devices use the additional clock cycles to decrypt and decompress the configuration data.  
Configuration Scheme  
Decompression  
Disabled  
Disabled  
Enabled  
Design Security  
Disabled  
Enabled  
DCLK-to-DATA[] Ratio  
1
1
2
2
1
2
4
4
1
4
8
8
FPP ×8  
Disabled  
Enabled  
Enabled  
Disabled  
Disabled  
Enabled  
Disabled  
Enabled  
FPP ×16  
FPP ×32  
Disabled  
Enabled  
Enabled  
Disabled  
Disabled  
Enabled  
Disabled  
Enabled  
Disabled  
Enabled  
Enabled  
Arria V GZ Device Datasheet  
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Altera Corporation  
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