AV-51002
2017.02.10
2-23
Transceiver Clocks
Unit
Transceiver Speed Grade 2
Transceiver Speed Grade 3
Symbol/Description
Conditions
Min
—
—
—
—
—
—
Typ
—
—
—
—
—
—
Max
-70
Min
—
—
—
—
—
—
Typ
—
—
—
—
—
—
Max
100 Hz
1 kHz
-70
-90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps (rms)
-90
Transmitter REFCLK Phase
Noise (622 MHz) (141)
10 kHz
100 kHz
≥1 MHz
-100
-110
-120
3
-100
-110
-120
3
Transmitter REFCLK Phase
Jitter (100 MHz) (142)
10 kHz to 1.5 MHz
(PCIe)
RREF
—
—
1800 1%
—
—
1800 1%
—
Ω
Related Information
Arria V Device Overview
For more information about device ordering codes.
Transceiver Clocks
Table 2-23: Transceiver Clocks Specifications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. e maximum data rate could be restricted by the Core/PCS speed
grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more
information about device ordering codes, refer to the Arria V Device Overview.
(141)
(142)
To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz) =
REFCLK phase noise at 622 MHz + 20*log(f/622).
To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
Arria V GZ Device Datasheet
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