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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
2-20  
I/O Standard Specifications  
VCCIO (V) (128)  
VID (mV) (129)  
Condition  
VICM(DC) (V)  
Condition  
VOD (V) (130)  
Typ  
VOCM (V) (130)  
I/O Standard  
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Typ  
Max  
RSDS  
2.375  
2.5  
2.625  
100  
VCM  
=
0.3  
1.4  
0.1  
0.2  
0.6  
0.5  
1.2  
1.4  
(HIO)  
1.25 V  
(133)  
Mini-  
LVDS  
2.375  
2.5  
2.625  
200  
600  
0.4  
1.325  
0.25  
0.6  
1
1.2  
1.4  
(HIO)  
(134)  
300  
300  
0.6  
1
DMAX  
1.8  
1.6  
700 Mbps  
LVPECL  
(135) (136)  
,
DMAX  
700 Mbps  
>
Related Information  
Glossary on page 2-73  
(128)  
(129)  
(130)  
(133)  
(134)  
(135)  
(136)  
Differential inputs are powered by VCCPD which requires 2.5 V.  
e minimum VID value is applicable over the entire common mode range, VCM.  
RL range: 90 ≤ RL ≤ 110 Ω.  
For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V.  
For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.3 V to 1.425 V.  
LVPECL is only supported on dedicated clock input pins.  
For optimized LVPECL receiver performance, the receiver voltage input range must be between 0.85 V to 1.75 V for data rate above 700 Mbps and  
0.45 V to 1.95 V for data rate below 700 Mbps.  
Arria V GZ Device Datasheet  
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Altera Corporation  
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