欢迎访问ic37.com |
会员登录 免费注册
发布采购

5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第125页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第126页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第127页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第128页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第130页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第131页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第132页浏览型号5ASXMB3E4F31I3N的Datasheet PDF文件第133页  
AV-51002  
2017.02.10  
2-25  
Receiver  
Transceiver Speed Grade 2  
Transceiver Speed Grade 3  
Symbol/Description  
Conditions  
Unit  
Min  
Typ  
Max  
Min  
Typ  
Max  
Maximum peak-to-peak differential  
input voltage VID (diff p-p) before  
device configuration  
1.6  
1.6  
V
VCCR_GXB = 1.0 V  
(VICM = 0.75 V)  
85  
1.8  
2.4  
85  
1.8  
2.4  
V
V
Maximum peak-to-peak differential  
input voltage VID (diff p-pꢁ)afer  
device configuration (146)  
VCCR_GXB = 0.85 V  
(VICM = 0.6 V)  
Minimum differential eye opening at  
mV  
Ω
receiver serial input pins (147)(148)  
85−Ω setting  
100−Ω setting  
120−Ω setting  
150−Ω setting  
85 30%  
85  
30%  
100  
30%  
100  
30%  
Ω
Differential on-chip termination  
resistors  
120  
30%  
120  
30%  
Ω
150  
30%  
150  
30%  
Ω
(146)  
e maximum peak to peak differential input voltage VID afer device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).  
(147)  
e differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equaliza‐  
tion, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.  
Minimum eye opening of 85 mV is only for the unstressed input eye condition.  
(148)  
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation  
 复制成功!