AV-51001
2013.05.06
21
FPGA General Purpose I/O
• Reference clock switchover
• Programmable bandwidth
• Dynamic phase shift
• Zero delay buffers
Fractional PLL
In addition to integer PLLs, the Arria V devices use a fractional PLL architecture. The devices have up to 16
PLLs, each with 18 output counters. One fractional PLL can use up to 18 output counters and two adjacent
fractional PLLs share the 18 output counters. You can use the output counters to reduce PLL usage in two
ways:
• Reduce the number of oscillators that are required on your board by using fractional PLLs
• Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies
from a single reference clock source
If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency
synthesis—removing the need for off-chip reference clock sources in your design.
The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose
fractional PLLs by the FPGA fabric.
FPGA General Purpose I/O
Arria V devices offer highly configurable GPIOs. The following list describes the features of the GPIOs:
• Programmable bus hold and weak pull-up
• LVDS output buffer with programmable differential output voltage (VOD ) and programmable
pre-emphasis
• On-chip parallel termination (RT OCT) for all I/O banks with OCT calibration to limit the termination
impedance variation
• On-chip dynamic termination that has the ability to swap between series and parallel termination,
depending on whether there is read or write on a common bus for signal integrity
• Unused voltage reference ( VREF ) pins that can be configured as user I/Os (Arria V GX, GT, SX, and
ST only)
• Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop
(DLL) delay chain with fine and coarse architecture
PCIe Gen1, Gen2, and Gen 3 Hard IP
Arria V devices contain PCIe hard IP that is designed for performance, ease-of-use, and increased
functionality. The PCIe hard IP consists of the MAC, data link, and transaction layers.
The PCIe hard IP supports PCIe Gen3, Gen 2, and Gen 1 end point and root port for up to x8 lane
configuration.
The PCIe endpoint support includes multifunction support for up to eight functions, as shown in the
following figure. The integrated multifunction support reduces the FPGA logic requirements by up to
20,000 LEs for PCIe designs that require multiple peripherals.
Arria V Device Overview
Altera Corporation
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