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5AGXMA3D631C4N 参数 Datasheet PDF下载

5AGXMA3D631C4N图片预览
型号: 5AGXMA3D631C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件概述 [Arria V Device Overview]
分类和应用:
文件页数/大小: 37 页 / 793 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51001  
2013.05.06  
23  
HPS External Memory Performance  
Soft Controller (MHz)  
Hard Controller (MHz)  
Interface  
Voltage (V)  
Arria V GX, GT, SX, and Arria V GX, GT, SX, and  
Arria V GZ  
ST  
ST  
1.8  
1.5  
1.8  
1.5  
1.8  
1.5  
1.8  
1.5  
400  
400  
400  
400  
400  
400  
400  
400  
533  
533  
500  
500  
333  
333  
RLDRAM II  
QDR II+ SRAM  
QDR II SRAM  
DDR II+ SRAM18  
HPS External Memory Performance  
Table 19: HPS External Memory Interface Performance  
The hard processor system (HPS) is available in Arria V SoC FPGA devices only.  
Interface  
Voltage (V)  
1.5  
HPS Hard Controller (MHz)  
533  
533  
400  
400  
333  
DDR3 SDRAM  
DDR2 SDRAM  
1.35  
1.8  
1.5  
LPDDR2 SDRAM  
1.2  
Low-Power Serial Transceivers  
Arria V devices deliver the industry's lowest power consumption per transceiver channel:  
12.5 Gbps transceivers at less than 170 mW  
10 Gbps transceivers at less than 165 mW  
6 Gbps transceivers at less than 105 mW  
Arria V transceivers are designed to be compliant with a wide range of protocols and data rates.  
Transceiver Channels  
The transceivers are positioned on the left and right outer edges of the device. The transceiver channels  
consist of the physical medium attachment (PMA), physical coding sublayer (PCS), and clock networks.  
18  
Not available as Altera® IP.  
Arria V Device Overview  
Altera Corporation  
Feedback  
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