AV-51001
2013.05.06
24
Transceiver Channels
The following figures are graphical representations of a top view of the silicon die, which corresponds to a
reverse view for flip chip packages. Different Arria V devices may have different floorplans than the ones
shown in the figures.
Figure 9: Device Chip Overview for Arria V GX and GT Devices
I/O, LVDS, and Memory Interface
Hard Memory Controller
Hard Transceiver
PCS
Hard Transceiver
PCS PMA
Hard Transceiver
PCS PMA
PMA
Transceiver
Individual Channels
Core Logic Fabric
and MLABs
M10K Internal
Memory Blocks
Variable-Precision
DSP Blocks
Hard Memory Controller
I/O, LVDS, and Memory Interface
Arria V Device Overview
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