Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Single Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Table 37.
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
True RSDS transmitter is only supported at bottom I/O banks. Emulated RSDS transmitter is supported at the output pin of all I/O banks.
Symbol
Parameter
Mode
–I6, –A6, –C7, –I7
Min Max
–A7
Typ
—
–C8
Typ
—
Unit
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
5
Max
50
Min
5
Max
50
fHSCLK
Input clock frequency
(high-speed I/O
performance pin)
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
5
5
50
50
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
5
—
50
5
—
50
5
50
5
—
50
5
—
50
5
50
5
—
50
5
—
50
5
50
5
—
50
5
—
50
5
100
100
100
100
100
100
100
50
5
—
100
100
100
100
100
100
100
50
5
—
100
100
100
100
100
100
100
50
HSIODR
Data rate (high-speed
I/O performance pin)
100
80
70
40
20
10
5
100
80
70
40
20
10
5
—
100
80
70
40
20
10
5
—
—
—
—
—
—
—
—
—
—
—
fHSCLK
Input clock frequency
(low-speed I/O
performance pin)
—
—
5
50
5
—
50
5
—
50
5
50
5
—
50
5
—
50
5
50
5
—
50
5
—
50
5
50
5
—
50
5
—
50
5
100
100
5
—
100
100
5
—
100
100
HSIODR
Data rate (low-speed
I/O performance pin)
100
100
—
100
—
continued...
Intel® MAX® 10 FPGA Device Datasheet
38
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