Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Hysteresis Specifications for Schmitt Trigger Input
Intel MAX 10 devices support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the input
signal for improved noise immunity, especially for signal with slow edge rate.
Table 19.
Hysteresis Specifications for Schmitt Trigger Input for Intel MAX 10 Devices
Symbol
Parameter
Condition
Minimum
180
Unit
mV
mV
mV
mV
VHYS
Hysteresis for Schmitt trigger input
VCCIO = 3.3 V
VCCIO = 2.5 V
VCCIO = 1.8 V
VCCIO = 1.5 V
150
120
110
(13)
The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is I/O pin capacitance and dv/dt
is the slew rate.
Intel® MAX® 10 FPGA Device Datasheet
16
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