AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
,
S
V
F
i
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
t
WC
Address
CS
t
(2)
t
(4)
CW
WR
t
AW
t
BW
UB,LB
WE
t
(1)
WP
t
DH
t
(3)
t
AS
DW
High-Z
High-Z
Data in
Data Valid
t
WHZ
t
OW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
t
WC
Address
CS
t
(3)
t
(2)
AS
tWR(4)
CW
t
AW
t
BW
UB,LB
t
(1)
WP
WE
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
7