AUGUST 2010
AS6C8016A
512K X 16 BIT LOW POWER CMOS SRAM
E
6
P
V
5
K
1
S
A
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
t
RC
Address
Data Out
t
AA
t
OH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH
)
t
RC
Address
CS
t
AA
t
OH
t
CO
t
HZ
t
t
BA
UB,LB
t
t
BHZ
OHZ
OE
OE
t
OLZ
High-Z
Data Out
Data Valid
t
BLZ
t
LZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
