AS4LC4M16S0
AS4LC16M4S0
®
Package dimensions
c
54-pin TSOP II
34 33 32 31 30 29 28
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
Min
Max
(mm)
(mm)
A
–
1.2
–
54-pin TSOP II
E He
A
0.05
0.95
0.30
0.12
22.12
10.03
1
A
1.05
0.45
0.21
22.32
10.29
2
b
c
D
E
e
21 22 23 24 25 26 27
1
2
3
4
5
6
7
8
9 10 11 12 13 1415 16 17 18 19 20
D
l
0.80 (typical)
11.56
0.40
11.96
0.60
He
l
A
2
A
0–5°
A
1
b
e
AC test conditions
- Input reference levels of VIH = 2.0V and VIL = 0.8V
- Output reference levels = 1.4V
- Input rise and fall times: 2 ns
+1.4V
50W
Z0 = 50W
D
OUT
C
= 50 pF
LOAD
Figure A: Equivalent output load
Ordering information
Part
–75
–8
–10
–10F
TSOP II, 400 mil, 54-pin
TSOP II, 400 mil, 54-pin
AS4LC8M8S0-75TC
AS4LC8M8S0-8TC
AS4LC8M8S0-10TC
AS4LC4M16S0-10TC
AS4LC8M8S0-10FTC
AS4LC4M16S0-10FTC
AS4LC4M16S0-75TC
AS4LC4M16S0-8TC
Part numbering system
AS4
LC
XXXS0
–XX
T
C
Device number for
synchronous DRAM
Package (device dependent):
TSOP II 400 mil, 54 pin
Commercial temperature
range, 0° C to 70 ° C
DRAM prefix LC = 3.3V CMOS
1/ frequency
24
ALLIANCE SEMICONDUCTOR
7/ 5/ 00
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
