1Gb DDR3L – AS4C128M8D3L
Figure 38. READ to PRECHARGE, RL = 5, AL = 0, CL = 5, tRTP = 4, tRP = 5
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK
NOP
READ
NOP
NOP
NOP
PRE
NOP
NOP
NOP
NOP
ACT
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
tRP
tRTP
RL = AL + CL
Bank a,
Col n
Bank a,
(or all)
Bank a,
Row b
BL4 Operation:
DQS, DQS#
DQ
DO
n
DO
n+1
DO
n+2
DO
n+3
BL8 Operation:
DQS, DQS#
DQ
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
NOTES:
1. RL = 5 (CL = 5, AL = 0)
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes tRAS.MIN is satisfied at Precharge command time (T5) and that tRC.MIN is satisfied at the next Active command time (T10).
TRANSITIONING DATA
Don't Care
Figure 39. READ to PRECHARGE, RL = 8, AL = CL-2, CL = 5, tRTP = 6, tRP = 5
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
NOP
NOP
NOP
NOP
ACT
COMMAND
ADDRESS
tRTP
tRP
AL = CL - 2 = 3
CL = 5
Bank a,
Col n
Bank a,
(or all)
Bank a,
Row b
BL4 Operation:
DQS, DQS#
DQ
DO
DO
DO
DO
n
n+1
n+2
n+3
BL8 Operation:
DQS, DQS#
DQ
DO
n
DO
n+1
DO
n+2
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
NOTES:
1. RL = 8 (CL = 5, AL = CL - 2)
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes tRAS.MIN is satisfied at Precharge command time (T10) and that tRC.MIN is satisfied at the next Active command time (T15).
TRANSITIONING DATA
Don't Care
Confidential
69
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
