1Gb DDR3L – AS4C128M8D3L
Figure 40. Write Timing Definition and parameters
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
Notes 3
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
WL = AL + CWL
Notes 4
Bank
Col n
ADDRESS
tDSH
tDSH
tWPST(min)
t
DQSS tDSH
tDSH
tWPRE(min)
tDQSS(min)
DQS, DQS#
tDQSH(min)
tDQSL
tDSS
tDQSH
tDQSH
tDQSL
tDSS
tDQSL
tDSS
tDQSL
tDSS
tDQSH tDQSL(min)
tDSS
tDQSH
Notes 2
Din
n
Din
n+2
Din
n+3
Din
n+4
Din
n+6
Din
n+7
DQ
DM
tWPST(min)
tDQSS(nominal)
tDSH
tDSH
tDSH
tDSH
tWPRE(min)
DQS, DQS#
tDQSH(min)
tDQSL
tDSS
tDQSL
tDSS
tDQSL
tDSS
tDQSL
tDSS
tDQSH
tDQSH
tDQSH
tDQSH tDQSL(min)
tDSS
Notes 2
Din
n
Din
n+2
Din
n+3
Din
n+4
Din
n+6
Din
n+7
DQ
DM
tDQSS
tDSH
tWPST(min)
tDSH
tDSH
tDSH
tDQSS(max)
tWPRE(min)
DQS, DQS#
tDQSH(min)
tDQSL
tDSS
tDQSL tDQSH
tDSS
tDQSH tDQSL
tDSS
tDQSH tDQSL
tDSS
tDQSL(min)
tDQSH
tDSS
Notes 2
Din
n
Din
n+2
Din
n+3
Din
n+4
Din
n+6
Din
n+7
DQ
DM
NOTES:
1. BL8, WL = 5 (AL = 0, CWL = 5)
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
5. tDQSS must be met at each rising clock edge.
TRANSITIONING DATA
Don't Care
Confidential
70
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
