1Gb DDR3L – AS4C128M8D3L
Figure 27. MPR Readout of predefined pattern,BC4 lower nibble then upper nibble
CK#
T0
Ta
Tb
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Td
CK
tMPRR
tMOD
PREA
MRS
READ
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
VALID
COMMAND
BA
Notes 1
Notes 1
tRP
tMOD
tCCD
3
0
VALID
VALID
3
VALID
0
A[1:0]
A[2]
0
0
Notes 2
Notes 2
1
0
1
Notes 4
Notes 3
00
VALID
VALID
00
A[9:3]
A10, AP
1
0
0
VALID
VALID
VALID
VALID
0
0
A[11]
0
0
VALID
VALID
0
0
A12, BC#
A[14:13]
DQS, DQS#
DQ
Notes 1
Notes 1
VALID
VALID
RL
RL
NOTES:
1. RD with BC4 either by MRS or OTF.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
TIME BREAK
Don't Care
Figure 28. MPR Readout of predefined pattern,BC4 upper nibble then lower nibble
CK#
T0
Ta
Tb
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Td
CK
tMPRR
tMOD
PREA
MRS
READ
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
VALID
COMMAND
BA
Notes 1
Notes 1
tRP
tMOD
tCCD
3
0
VALID
VALID
3
VALID
0
0
0
A[1:0]
A[2]
Notes 2
Notes 2
1
1
0
Notes 3
Notes 4
00
VALID
VALID
00
A[9:3]
A10, AP
A[11]
0
0
VALID
VALID
VALID
VALID
0
0
1
A12, BC#
0
0
VALID
VALID
0
0
Notes 1
Notes 1
VALID
VALID
A[14:13]
DQS, DQS#
DQ
RL
RL
NOTES:
1. RD with BC4 either by MRS or OTF.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
TIME BREAK
Don't Care
Confidential
65
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
