[AK4671]
CONTROL SEQUENCE (AUDIO)
Clock Set up
When ADC or DAC is powered-up, the clocks must be supplied.
1. PLL Master Mode.
Example:
Power Supply
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
(1)
PDN pin
(2)
(3)
Sampling Frequency: 44.1kHz
PMVCM bit
(Addr:00H, D0)
(4)
(1) Power Supply & PDN pin = “L” Æ “H”
MCKO bit
(Addr:02H, D2)
PMPLL bit
(2)Addr:02H, Data:22H
Addr:03H, Data:02H
Addr:01H, Data:F4H
(Addr:02H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:01H
(4)Addr:02H, Data:27H
(Addr:02H, D1)
40msec(max)
(6)
(8)
BICK pin
LRCK pin
Output
Output
40msec(max)
(7)
MCKO, BICK and LRCK output
MCKO pin
Figure 109. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
(5) PLL lock time is 40ms(max.) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(6) The AK4671 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation
starts.
(7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”.
MS0666-E-02
2010/06
- 147 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
