[AK4671]
SYSTEM DESIGN
Figure 108 shows the system connection diagram for the AK4671. The evaluation board [AKD4671] demonstrates the
optimum layout, power supply arrangements and measurement results.
Headphone
Analog
Ground
Digital
Ground
Digital
(Base Band)
1.6 ∼ 3.6V
10u
Analog
2.2 ∼ 3.6V
Base Band
0.1u
TEST
AVDD
RCP
LOUT2 ROUT2 VCOM VCOCBT VSS2
SDTOA SYNCA GPO2
Digital
(μP & CPU)
1.6 ∼ 3.6V
VSS1
RCN
MUTET VCOC
PVDD TVDD2 BICKA
CDTI
VSS4
CCLK
I2C
SDTIA
DVDD
CSN
Receiver
Ext SPK-Amp
0.1u
μP
Stereo
Speaker
ROUT3 LOUT3
AK4671EG
Top View
RIN4
LIN3
IN2+
IN1+
MDT
LIN4
RIN3
IN2−
IN1−
BICK
Line In
MCKI
PDN
MCKO
LRCK
CDTO
GPO1
CPU
External MIC
Internal MIC
NC
SAIN2 SAVDD TVDD3 SDTOB BICKB
SDTO
SDTI
MPWR SAIN3
SAIN1
VSS3
SYNCB SDTIB
Bluetooth
Module
Digital
(Bluetooth)
1.6 ∼ 3.6V
DC Measurement
Notes:
- VSS1, VSS2, VSS3 and VSS4 of the AK4671 should be distributed separately from the ground of external
controllers.
- All digital input pins should not be left floating.
- When the AK4671 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC pin is not needed.
- When the AK4671 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC pin is shown in Table
4.
- When the AK4671 is used by master mode, LRCK and BICK pins are a Hi-Z state until M/S bit becomes “1”.
LRCK and BICK pins of the AK4671 should be pulled-down or pulled-up by the resistor (about 100kΩ)
externally to avoid the floating state.
- A resistor and capacitor of the VCOCBT pin is shown in Table 76.
- After setting PDN pin = “H”, the PCM I/F clock pins of AK4671 are a Hi-Z state until PMPCM bit becomes
“1”. The PCM I/F clock pins of master mode should be pulled-down or pulled-up by the resistor (about 100kΩ)
externally to avoid the floating state.
Figure 108. Typical Connection Diagram
(Internal Full-differentila Mic, External pseudo differential Mic, Recevier Output, 4-wire serial mode)
MS0666-E-02
2010/06
- 145 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
