[AK4671]
1. Grounding and Power Supply Decoupling
The AK4671 requires careful attention to power supply and grounding arrangements. AVDD, PVDD, SAVDD, DVDD,
TVDD2 and TVDD3 are usually supplied from the system’s analog supply. If AVDD, PVDD, SAVDD, DVDD, TVDD2
and TVDD3 are supplied separately, the power-up sequence is not critical. The PDN pin should be held to “L” when
power-up. The PDN pin should be set to “H” after all power supplies are powered-up.
In case that the pop noise should be avoided at receiver output, headphone output and line output, the AK4671 should be
operated by the following recommended power-up/down sequence.
1) Power-up
- The PDN pin should be held to “L” when power-up. The AK4671 should be reset by bringing the PDN pin “L” for
150ns or more.
- In case that the power supplies are separated in two or more groups, the power supply including DVDD should be
powered ON at first.
2) Power-down
- Each power supplies should be powered OFF after the PDN pin is set to “L”.
- In case that the power supplies are separated in two or more groups, the power supply including DVDD should be
powered OFF at last.
VSS1, VSS2, VSS3 and VSS4 of the AK4671 should be connected to the analog ground plane. System analog ground
and digital ground should be connected together near to where the supplies are brought onto the printed circuit board.
Decoupling capacitors should be as near to the AK4671 as possible, with the small value ceramic capacitor being the
nearest.
2. Voltage Reference
VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor attached
to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All
signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the
AK4671.
3. Analog Inputs
The Mic, Line and MIN inputs are single-ended. The input signal range scales with nominally at 0.6 x AVDD Vpp (typ)
at MGNL=MGNR=0dB and single-ended input, centered around the internal common voltage (0.5 x AVDD). The input
signal should be AC coupled using a capacitor. The cut-off frequency is fc = 1/(2πRC). The AK4671 can accept input
voltages from VSS1 to AVDD.
4. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and
a negative full scale for 8000H(@16bit). The ideal output is VCOM voltage for 0000H(@16bit). VCOM voltage is 0.5 x
AVDD (typ).
When LOUT1, ROUT1, LOUT2, ROUT2, LOUT3/LOP and ROUT3/LON pins are single-ended output, these pins
should be AC coupled using a capacitor. When RCP, RCN pins are full-differential output, these pins should be
connected directly to a receiver. (RCP, RCN pins should be not AC coupled using a capacitor.)
MS0666-E-02
2010/06
- 146 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
