[AK4671]
D0
Addr Register Name
D7
SDOAD
R/W
0
D6
BCKO2
R/W
0
D5
MSBSA
R/W
0
D4
BCKPA
R/W
0
D3
D2
D1
54H
PCM I/F Control 2
R/W
LAWA1 LAWA0 FMTA1 FMTA0
R/W
0
R/W
0
R/W
0
R/W
0
Default
FMTA1-0: PCM I/F A Format (Table 84)
Default: “00” (Mode 0)
LAWA1-0: PCM I/F A Mode (Table 82)
Default: “00” (Mode 0)
BCKPA: BICKA Polarity of PCM I/F A (Table 86)
“0”: SDTOA is output by the rising edge (“↑”) of BICKA and SDTIA is latched by the falling edge (“↓”). (default)
“1”: SDTOA is output by the falling edge (“↓”) of BICKA and SDTIA is latched by the rising edge (“↑”).
MSBSA: SYNCA Phase of PCM I/F A (Table 86)
“0”: The rising edge (“↑”) of SYNCA is half clock of BICKA before the channel change. (default)
“1”: The rising edge (“↑”) of SYNCA is one clock of BICKA before the channel change.
BCKO2: BICKA/B Output Frequency Select at Master Mode (Table 77)
0: 16fs2 (default)
1: 32fs2
SDOAD: SDTOA Disable (Table 56)
“0”: Enable (default)
“1”: Disable (“L”)
Addr Register Name
D7
SDOBD
R/W
0
D6
PLLBT3
R/W
D5
MSBSB
R/W
0
D4
BCKPB
R/W
0
D3
D2
D1
D0
55H
PCM I/F Control 3
R/W
LAWB1 LAWB0 FMTB1 FMTB0
R/W
0
R/W
0
R/W
0
R/W
0
Default
0
FMTB1-0: PCM I/F B Format (Table 85)
Default: “00” (Mode 0)
LAWB1-0: PCM I/F B Mode (Table 83)
Default: “00” (Mode 0)
BCKPB: BICKB Polarity of PCM I/F B (Table 87)
“0”: SDTOB is output by the rising edge (“↑”) of BICKB and SDTIB is latched by the falling edge (“↓”). (default)
“1”: SDTOB is output by the falling edge (“↓”) of BICKB and SDTIB is latched by the rising edge (“↑”).
MSBSB: SYNCB Phase of PCM I/F B (Table 87)
“0”: The rising edge (“↑”) of SYNCB is half clock of BICKB before the channel change. (default)
“1”: The rising edge (“↑”) of SYNCB is one clock of BICKB before the channel change.
PLLBT3: PLLBT Reference Clock Select (Table 76)
PLLBT2-0 bits is D5-3 of Addr=53H.
Default: “0000”: SYNCA
SDOBD: SDTOB Disable (Table 58)
“0”: Enable (default)
“1”: Disable (“L”)
MS0666-E-02
2010/06
- 142 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
