[AK4679]
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
9
10
11
12 13
14 15
16
17
24
25 26
27
26 29
30 31
0
2
18
BICK(32fs)
SDTO(o)
Lch
15
Rch
0
0
8
8
7
7
6
6
5
5
4
4
3
2
2
1
0
0
15
8
8
7
7
6
5
5
4
4
3
2
2
1
0
0
14
14
Lch
15
Rch
15
3
1
6
3
1
14
14
SDTI(i)
15
0
1
14
15 16
17
18
30 31
32 33
46
47 48
49
50
62 63
2
34
BICK(64fs)
SDTO(o)
Lch
15
Rch
15
2
2
1
1
0
0
2
1
1
0
0
14
14
14
14
Lch
15
Rch
15
2
SDTI(i)
1/fs
15:MSB, 0:LSB
Figure 46. Mode 0 Timing (BCKP bit = “0”, MSBS bit = “0”)
LRCK
(Master)
LRCK
(Slave)
15
0
1
8
9
10
11
12 13
14 15
16
17
24
25 26
27
26 29
30 31
0
2
18
BICK(32fs)
SDTO(o)
Lch
15
Rch
0
0
8
8
7
7
6
6
5
5
4
4
3
2
2
1
0
0
15
8
8
7
7
6
5
5
4
4
3
2
2
1
0
0
14
14
Lch
15
Rch
15
3
1
6
3
1
14
14
SDTI(i)
15
0
1
14
15 16
17
18
30 31
32 33
46
47 48
49
50
62 63
2
34
BICK(64fs)
SDTO(o)
Lch
15
Rch
15
2
2
1
1
0
0
2
1
1
0
0
14
14
14
14
Rch
Lch
15
15
2
SDTI(i)
1/fs
15:MSB, 0:LSB
Figure 47. Mode 0 Timing (BCKP bit = “1”, MSBS bit = “0”)
MS1402-E-06
2013/02
- 57 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
