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AK4675 参数 Datasheet PDF下载

AK4675图片预览
型号: AK4675
PDF下载: 下载PDF文件 查看货源
内容描述: 立体声编解码器与MIC / RCV / HP / SPK- AMP [Stereo CODEC with MIC/RCV/HP/SPK-AMP]
分类和应用: 解码器编解码器
文件页数/大小: 178 页 / 2136 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4675]  
System Clock (PCM I/F)  
A reference clock of PLLBT is selected among the input clocks to the SYNCA, BICKA, SYNCB or BICKB pin. The  
required clock to PCM I/F is generated by an internal PLLBT circuit. PLLBT circuit is powered up by PMPCM bit. Input  
frequency is selected by PLLBT3-0 bits (Table 95). BCKO2 bit select the output clock frequency of the BICKA or  
BICKB pin (Table 96).  
The AK4675 does not support master mode for both PCM I/F A and B nor slave mode for both PCM I/F A and B.  
Whether PCM I/F A or B should be set as slave mode. When PMPCM bit is “0”, SYNCA, BICKA, SYNCB and BICKB  
pins are Hi-Z. Table 97 indicates the output data of the SDTOA and SDTOB pins in case of PMPCM bit = “0” and during  
lock time in Table 95, respectively. Table 98 indicates the output clock at master mode during lock time in Table 95.  
The AK4675 does not support master mode for both PCM I/F A and B nor slave mode for both PCM I/F A and B. When  
PMPCM bit is “0”, the SYNCA, BICKA, SYNCB and BICKB pins are Hi-Z.  
R, C at  
VCOCBT pin  
Reference Clock  
Input Pin  
Lock Time  
(max)  
Mode  
PLLBT3 PLLBT2 PLLBT1 PLLBT0  
Frequency  
R
C
0
1
2
3
4
5
6
7
11  
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
1
1
SYNCA  
BICKA  
BICKA  
BICKA  
SYNCB  
BICKB  
BICKB  
BICKB  
BICKA  
BICKB  
N/A  
1fs2  
16fs2  
32fs2  
64fs2  
1fs2  
16fs2  
32fs2  
64fs2  
48fs2  
48fs2  
6.8k  
10k  
10k  
10k  
6.8k  
10k  
10k  
10k  
10k  
10k  
220n  
4.7n  
4.7n  
4.7n  
220n  
4.7n  
4.7n  
4.7n  
4.7n  
4.7n  
260ms  
40ms  
40ms  
40ms  
260ms  
40ms  
40ms  
40ms  
40ms  
40ms  
(default)  
15  
Others  
Note 83. Mode 1 is available at only FMTA1 bit = “0”.  
Note 84. Mode 5 is available at only FMTB1 bit = “0”.  
Table 95. PLLBT Reference Clock  
BICKA/BICKB  
Output Frequency  
16fs2  
BCKO2 bit  
0
1
(default)  
32fs2  
Table 96. BICKA/B Output Frequency  
PMPCM bit = “1”  
During Lock time  
After PMPCM bit = “0” “1”  
& Before SYNCA/SYNCB Input  
Mode  
PMPCM bit = “0”  
16bit Linear  
8bit A-Law  
8bit μ-Law  
L
L
L
L
H
H
“0000H”  
“11010101b”  
“11111111b”  
Table 97. SDTOA, SDTOB pins Output Data  
Format  
SYNCA, SYNCB  
BICKA, BICKB  
Except for I2S  
I2S  
L
H
L
L
Table 98. Output Clock during Lock Time  
MS0963-E-00  
2008/05  
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