[AK4675]
■ PCM I/F A & B Format
The AK4675 supports dual PCM I/F (PCM I/F A & PCM I/F B) that supports 3 kind of I/F (16bit Linear, 8bit A-Law and
8bit μ-Law) independently (Table 101, Table 102).
Mode
LAWA1
LAWA0
Format
16bit Linear
N/A
8bit A-Law
8bit μ-Law
0
1
2
3
0
0
1
1
0
1
0
1
(default)
(default)
Table 101. PCM I/F A Mode
Mode
LAWB1
LAWB0
Format
0
1
2
3
0
0
1
1
0
1
0
1
16bit Linear
N/A
8bit A-Law
8bit μ-Law
Table 102. PCM I/F B Mode
Four types of data formats are available and are selected by setting the FMTA1-0 and FMTB1-0 bits independently (Table
103, Table 104). In 16bit Linear mode, the serial data is MSB first, 2’s complement format. In 8bit A-Law and μ-Law
Mode, the serial data is MSB first. PCM I/F formats can be used in both master and slave modes. SYNCA/B and
BICKA/B are output from the AK4675 in master mode, but must be input to the AK4675 in slave mode.
Mode
FMTA1
FMTA0
Format
Short Frame Sync
Long Frame Sync
MSB justified
I2S
BICKA
≥ 16fs2
≥ 16fs2
≥ 32fs2
≥ 32fs2
Figure
0
1
2
3
0
0
1
1
0
1
0
1
See Table 105 (default)
See Table 107
Figure 99
Figure 100
Table 103. PCM I/F A Format
Mode
FMTB1
FMTB0
Format
Short Frame Sync
Long Frame Sync
MSB justified
I2S
BICKB
Figure
0
1
2
3
0
0
1
1
0
1
0
1
See Table 106 (default)
See Table 108
Figure 99
≥ 16fs2
≥ 16fs2
≥ 32fs2
≥ 32fs2
Figure 100
Table 104. PCM I/F B Format
In modes 2/ 3, the SDTOA/B is clocked out on the falling edge (“↓”) of BICKA/B and the SDTIA/B is latched on the
rising edge (“↑”).
In Modes 0 and 1, PCM I/F A timing is changed by BCKPA and MSBSA bits, and PCM I/F B timing is changed by
BCKPB and MSBSB bits.
When BCKPA bit = “0”, the SDTOA is clocked out on the rising edge (“↑”) of BICKA and the SDTIA is latched on the
falling edge (“↓”). When BCKPA bit = “1”, the SDTOA is clocked out on the falling edge (“↓”) of BICKA and the
SDTIA is latched on the rising edge (“↑”).
MSBSA bit can shift the MSB position of SDTOA and SDTIA by half period of BICKA.
When BCKPB bit = “0”, the SDTOB is clocked out on the rising edge (“↑”) of BICKB and the SDTIB is latched on the
falling edge (“↓”). When BCKPB bit = “1”, the SDTOB is clocked out on the falling edge (“↓”) of BICKB and the
SDTIB is latched on the rising edge (“↑”).
MSBSB bit can shift the MSB position of SDTOB and SDTIB by half period of BICKB.
MS0963-E-00
2008/05
- 126 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
