[AK4675]
a) PLLBT reference clock: SYNCA or BICKA pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCA or BICKA. Generated clocks are output via
the SYNCB and BICKB pins.
AK4675
Phone Module
1fs2
SYNCA
SYNC
≥ 16fs2
BICK
SDTI
SDTO
BICKA
SDTOA
SDTIA
Bluetooth Module
1fs2
SYNC
SYNCB
16fs2 or 32fs2
BICK
SDTI
SDTO
BICKB
SDTOB
SDTIB
Figure 89. PCM I/F (PLLBT Reference Clock: SYNCA or BICKA pin)
b) PLLBT reference clock: SYNCB or BICKB pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCB or BICKB. Generated clocks are output via
the SYNCA and BICKA pins.
AK4675
Phone Module
1fs2
SYNCA
SYNC
16fs2 or 32fs2
BICK
SDTI
SDTO
BICKA
SDTOA
SDTIA
Bluetooth Module
1fs2
SYNC
SYNCB
≥ 16fs2
BICK
SDTI
SDTO
BICKB
SDTOB
SDTIB
Figure 90. PCM I/F (PLLBT Reference Clock: SYNCB or BICKB pin)
PLLBT should always be powered-up (PMPCM bit = “1”) whenever SRC-A or SRC-B is in operation (PMSRA bit = “1”
or PMSRB bit = “1”). If PLLBT is powered-down, the AK4675 may draw excess current and it is not possible to operate
properly because utilizes dynamic refreshed logic internally. If PLLBT is powered-down, SRC-A and SRC-B should be
in the power-down mode (PMSRA=PMSRB bits = “0”).
MS0963-E-00
2008/05
- 124 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
