[AK4675]
■ PCM I/F Master Mode/Slave Mode
The PLLBT2 bit selects either master or slave mode (Table 99). When either PCM I/F A or PCM I/F B is set in slave
mode, the other is set in master mode. (For example, when PCM I/F B is set in slave mode, PCM I/F A is set in master
mode.) When the AK4675 is power-down mode (PDN pin = “L”) or PMPCM bit = “0”, each clock pins (SYNCA,
BICKA, SYNCB, BICKB) of PCM I/F become a Hi-Z (Table 100).
PLLBT3-0 bits should be set when PMPCM bit = “0” to avoid shorting out of the slave mode clock pins and master mode
clock output.
After setting the PDN pin = “H”, the PCM I/F clock pins are the Hi-Z state until PMPCM bit becomes “1”. The PCM I/F
clock pins of master mode should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the
floating state.
PLLBT2 bit
PCM I/F A
Slave Mode
Master Mode
SYNCA, BICKA pins
PCM I/F B
Master Mode
Slave Mode
SYNCB, BICKB pins
0
1
Input
Output
Output
Input
(default)
Table 99. Select PCM I/F Master/Slave Mode
PDN pin
PMPCM bit
SYNCA, BICKA pin
SYNCB, BICKB pin
L
H
-
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I/O Select by PLLBT2 bit I/O Select by PLLBT2 bit
1
(Table 99)
(Table 100)
Table 100. PCM I/F Clock I/O State
MS0963-E-00
2008/05
- 125 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
