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AK4634EC 参数 Datasheet PDF下载

AK4634EC图片预览
型号: AK4634EC
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, PBGA29, 2.50 X 3 MM, 0.50 MM PITCH, CSP-29]
分类和应用: 商用集成电路
文件页数/大小: 87 页 / 1043 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4634]  
Parameter  
Symbol  
min  
typ  
max  
Units  
PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 6, Figure 7)  
FCK: Frequency  
DSP Mode: Pulse Width High  
Except DSP Mode: Duty Cycle  
BICK: Period  
fFCK  
tFCKH  
duty  
7.35  
8
-
-
-
-
-
48  
kHz  
ns  
tBCK60  
45  
1/fFCKtBCK  
55  
%
tBCK  
1/64fFCK  
0.4 x tBCK  
0.4 x tBCK  
1/16fFCK  
ns  
Pulse Width Low  
Pulse Width High  
tBCKL  
tBCKH  
-
-
ns  
ns  
PLL Slave Mode (PLL Reference Clock: BICK pin) (Figure 6, Figure 7)  
FCK: Frequency  
DSP Mode: Pulse width High  
fFCK  
tFCKH  
duty  
7.35  
8
48  
kHz  
ns  
tBCK60  
-
1/fFCKtBCK  
Except DSP Mode: Duty Cycle  
BICK: Period (PLL3-0 bit = “0001”)  
(PLL3-0 bit = “0010”)  
45  
-
55  
-
%
tBCK  
tBCK  
tBCK  
tBCKL  
tBCKH  
-
1/16fFCK  
ns  
-
1/32fFCK  
-
ns  
(PLL3-0 bit = “0011”)  
-
1/64fFCK  
-
ns  
Pulse Width Low  
0.4 x tBCK  
0.4 x tBCK  
-
-
-
ns  
Pulse Width High  
-
ns  
PLL Slave Mode (PLL Reference Clock: MCKI pin) (Figure 8)  
MCKI Input: Frequency  
Pulse Width Low  
Pulse Width High  
MCKO Output:  
fCLK  
fCLKL  
fCLKH  
12  
-
-
-
27.0  
MHz  
ns  
0.4/fCLK  
0.4/fCLK  
-
-
ns  
Frequency  
fMCK  
dMCK  
dMCK  
fFCK  
-
256 x fFCK  
-
kHz  
%
Duty Cycle except fs=29.4kHz, 32kHz  
fs=29.4kHz, 32kHz (Note 18)  
FCK: Frequency  
40  
-
50  
33  
-
60  
-
%
8
48  
kHz  
ns  
DSP Mode: Pulse width High  
Except DSP Mode: Duty Cycle  
BICK: Period  
tFCKH  
duty  
tBCK60  
45  
-
1/fFCKtBCK  
-
55  
%
tBCK  
1/64fFCK  
0.4 x tBCK  
0.4 x tBCK  
-
1/16fFCK  
ns  
Pulse Width Low  
tBCKL  
tBCKH  
-
-
-
ns  
Pulse Width High  
-
ns  
Audio Interface Timing  
DSP Mode: (Figure 9, Figure 10)  
FCK “” to BICK “” (Note 19)  
FCK “” to BICK “” (Note 20)  
BICK “” to FCK “” (Note 19)  
BICK “” to FCK “” (Note 20)  
BICK “” to SDTO (BCKP bit= “0”)  
BICK “” to SDTO (BCKP bit= “1”)  
SDTI Hold Time  
tFCKB  
tFCKB  
tBFCK  
tBFCK  
tBSD  
tBSD  
tSDH  
tSDS  
0.4 x tBCK  
0.4 x tBCK  
0.4 x tBCK  
0.4 x tBCK  
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
-
-
-
50  
50  
80  
80  
-
SDTI Setup Time  
-
Except DSP Mode: (Figure 12)  
FCK Edge to BICK “” (Note 21)  
BICK “” to FCK Edge (Note 21)  
FCK to SDTO (MSB) (Except I2S mode)  
BICK “” to SDTO  
tFCKB  
tBFCK  
tFSD  
tBSD  
tSDH  
tSDS  
50  
50  
-
-
50  
50  
-
-
-
-
-
-
-
-
80  
80  
-
ns  
ns  
ns  
ns  
ns  
ns  
SDTI Hold Time  
SDTI Setup Time  
-
MS0983-E-00  
2008/07  
- 11 -