[AK4634]
SWITING CHARACTERISTICS
(Ta = −30 ~ 85°C; AVDD = 2.2 ∼ 3.6V, DVDD = 1.6 ∼ 3.6V, SVDD = 2.2 ∼ 4.0V; CL = 20pF)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 2)
MCKI Input: Frequency
Pulse Width Low
Pulse Width High
MCKO Output:
fCLK
tCLKL
tCLKH
12
-
-
-
27.0
MHz
ns
0.4/fCLK
0.4/fCLK
-
-
ns
Frequency
fMCK
dMCK
dMCK
fFCK
-
40
-
256 x fFCK
-
kHz
%
Duty Cycle except fs=29.4kHz, 32kHz
fs =29.4kHz, 32kHz (Note 18)
FCK Output: Frequency
Pulse width High
50
33
-
60
-
%
8
48
kHz
(DIF1-0 bits = “00” and FCKO bit = “1”)
Duty Cycle
tFCKH
-
tBCK
-
ns
(DIF1-0 bits = “00” or FCKO bit = “0”)
BICK: Period (BCKO1-0 = “00”)
(BCKO1-0 = “01”)
dFCK
tBCK
tBCK
tBCK
dBCK
-
-
-
-
-
50
-
-
-
-
-
%
ns
ns
ns
%
1/16fFCK
1/32fFCK
1/64fFCK
50
(BCKO1-0 = “10”)
Duty Cycle
Audio Interface Timing
DSP Mode: (Figure 3, Figure 4)
FCK “↑” to BICK “↑” (Note 19)
FCK “↑” to BICK “↓” (Note 20)
BICK “↑” to SDTO (BCKP = “0”)
BICK “↓” to SDTO (BCKP = “1”)
SDTI Hold Time
tDBF
tDBF
tBSD
tBSD
tSDH
tSDS
0.5 x tBCK −40
0.5 x tBCK −40
0.5 x tBCK
0.5 x tBCK + 40
ns
ns
ns
ns
ns
ns
0.5 x tBCK
0.5 x tBCK +40
-70
-70
50
-
-
-
-
70
70
-
SDTI Setup Time
50
-
Except DSP Mode: (Figure 5)
BICK “↓” to FCK Edge
FCK to SDTO (MSB)
tBFCK
tFSD
−40
−70
-
-
40
70
ns
ns
(Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
tBSD
tSDH
tSDS
−70
50
-
-
-
70
-
ns
ns
ns
SDTI Setup Time
50
-
MS0983-E-00
2008/07
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
