[AK4634]
Parameter
Symbol
min
typ
max
Units
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN edge to CCLK “↑” (Note 23)
CCLK “↑” to CSN edge (Note 23)
CCLK “↓” to CDTIO (at Read Command)
CSN “↑” to CDTIO (Hi-Z) (at Read Command)
(Note 24)
tCSH
tDCD
tCCZ
-
-
70
ns
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
tBUF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
-
-
-
-
-
-
-
0.3
0.3
-
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 25)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
tF
tSU:STO
Cb
0.6
-
0
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
Reset Timing
PDN Pulse Width
PMADC “↑” to SDTO valid
(Note 26)
(Note 27)
tPD
150
-
-
ns
ADRST bit = “0”
ADRST bit = “1”
tPDV
tPDV
-
-
1059
291
-
-
1/fs
1/fs
Note 22. I2C is a registered trademark of Philips Semiconductors.
Note 23. CCLK rising edge must not occur at the same time as CSN edge.
Note 24. RL = 1kΩ/10% change ( Pull-up to DVDD)
Note 25. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 26. The AK4634 can be reset by the PDN pin = “L”
Note 27. This is the count of FCK “↑” from the PMADC = “1”.
MS0983-E-00
2008/07
- 14 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
