[AK4634]
■ Timing Diagram
1/fCLK
VIH
VIL
MCKI
tCLKH
tCLKL
dFCK
1/fFCK
50%DVDD
FCK
dFCK
1/fMCK
MCKO
50%DVDD
tMCKOH
tMCKOL
dMCK = tMCKOL x fMCK x 100%
Figure 2. Clock Timing (PLL/EXT Master mode) (MCKO is not available at EXT Master Mode)
FCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "0")
50%DVDD
50%DVDD
BICK
(BCKP = "1")
tBSD
SDTO
50%DVDD
MSB
tSDH
tSDS
VIH
VIL
SDTI
MSB
Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”)
MS0983-E-00
2008/07
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