[AK4492]
Pin
Name
SLOW
Protection
Diode
No.
E1
I/O
Function
I
I
Digital Filter Select Pin in Pin Control Mode (PSN pin = “H”)
Control Data Input Pin in Register Control Mode
(PSN pin = “L”, I2C pin = “L”)
Control Data Input Pin (PSN pin = “L”, I2C pin = “H”)
Digital Filter Select Pin in Pin Control Mode (PSN pin = “H”)
Control Data Clock Pin in Register Control Mode
(PSN pin = “L”, I2C pin = “L”)
CDTI
－ /DVSS
－ /DVSS
SDA
SD
I/O
I
E2
CCLK
I
SCL
VSSR
VSSR
I
-
-
Control Data Clock Input Pin (PSN pin = “L”, I2C pin = “H”)
Analog Ground Pin
Analog Ground Pin
E9
E10
-
-
Soft Mute Pin in Pin Control Mode (PSN pin = “H”)
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
SMUTE
I
F1
TVDD/DVSS Chip Select Pin in Register Control Mode
(PSN pin = “L”, I2C pin = “L”)
CSN
I
This Pin should be connected to DVSS
(PSN pin = “L”, I2C pin = “H”)
Audio Data Onput in Daisy Chain Mode
(Internal pull-down pin)
F2
TDMO
O
TVDD/DVSS
F9
F10
VSSL
VSSL
LRCK
DINR
DSDR
SSLOW
WCK
VDDL
VSSL
SDATA
DINL
-
-
I
I
I
I
I
-
-
I
I
I
-
-
Analog Ground Pin
Analog Ground Pin
L/R Clock Pin in PCM Mode
G1
TVDD/DVSS Rch Audio Data Input Pin in EXDF Mode
DSD Rch Data Input Pin in DSD Mode (DSDPATH bit = “1”)
Digital Filter Select Pin in Pin Control Mode (PSN pin= “H”)
Word Clock input Pin in EXDF Mode (PSN pin = “L”)
Lch Analog Power Supply Pin
Analog Ground Pin
Audio Data Input Pin in PCM Mode
G2
TVDD/DVSS
G9
G10
-
-
H1
H2
TVDD/DVSS Lch Audio Data Input Pin in EXDF Mode
DSD Lch Data Input Pin in DSD Mode (DSDPATH bit = “1”)
DSDL
Power-Up, Power-Down Pin
PDN
I
TVDD/DVSS When at “L”, the AK4492 is in power-down mode and is held in
reset.The AK4492 must always be reset upon power-up.
TVDD/DVSS Internal LDO Enable Pin. “L”: Disable, “H”: Enable
H3
H9
H10
LDOE
VDDL
VDDL
BICK
BCK
I
-
-
I
I
I
-
-
Lch Analog Power Supply Pin
Lch Analog Power Supply Pin
Audio Data Clock Pin in PCM Mode
J1
TVDD/DVSS Audio Data Clock Pin in EXDF Mode
DSD Clock Pin in DSD Mode (DSDPATH bit = “1”)
DCLK
Digital Power Supply Pin.
LDOE pin = “L”: (DVDD) ~ 3.6 V / LDOE pin = “H”: 3.0 ~ 3.6V
J2
TVDD
-
-
J3
J4
MCLK
AVSS
I
-
AVDD/AVSS Master Clock Input Pin
-
Analog Ground Pin
External Resistor Connect Pin
Rext=33 kΩ(±1 %, Note 1) toAVSS
Left channel Common Voltage Pin,
J5
EXTR
I
VDDL/VSSL
J8
VCML
-
VDDL/VSSL Normally connected to VREFLL with a 1 uF electrolytic cap. This
pin is inhibited to connect other devices.
J9 AOUTLP
O
VDDL/VSSL Lch Positive Analog Output Pin
016011073-E-00
2016/12
- 8 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
