[AK4492]
5. Pin Configurations and Functions
■ Pin Configurations
10
9
8
7
6
5
4
3
2
1
AK4492
Top View
A B C D E F G H J K
VDDR
VDDR
NC
VSSR
VDDR
NC
VSSR
VSSR
NC
VSSL
VSSL
NC
VSSL
VDDL
NC
VDDL
VDDL
NC
10
AOUTRN AOUTRP
AOUTLP AOUTLN
9
8
7
6
5
4
3
VREFLR
VREFLR
VREFHR
VREFHR
INVR
VCMR
NC
VCML
NC
VREFLL
VREFLL
VREFHL
VREFHL
AVDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TESTE
DCHAIN
TDM1
NC
NC
NC
NC
NC
NC
EXTR
AVSS
MCLK
NC
NC
NC
NC
NC
NC
TDM0/
DCLK
NC
PSN
NC
NC
NC
LDOE
DVDD
SD/
CCLK/
SCL
SLOW/
CDTI/
SDA
ACKS/
CAD1
GAIN/
DSDR
HLOAD/
I2C
DIF2/
CAD0
SSLOW/
WCK
TDMO
PDN
TVDD
DVSS
2
1
LRCK/
DINR/
DSDR
SDATA/
DINL/
DSDL
BICK/
BCK/
DCLK
DEM0/
DSDL
DIF1/
DZFR
DIF0/
DZFL
SMUTE/
CSN
NC
NC
A
B
C
D
E
F
G
H
J
K
Figure 2. Pin Configurations
The exposed pad on the bottom surface of the package must be connected to VSS.
016011073-E-00
2016/12
- 6 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
