[AK4492]
If RSTN bit is set to “0”, the output signal of the DZFL/R pin becomes “H”. Then, the DAC is reset after 3~
4/fs and the analog output becomes the same voltage as VCML/R. The synchronize function becomes
valid when both of the DZFL and the DZFR pins output “H”.
RSTN bit
3~4/fs (4)
2~3/fs (4)
Internal
RSTN bit
Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
D/A In
(Digital)
force”0”
(2)
(3)
GD
GD
(3)
(5)
(5)
D/A Out
(Analog)
2/fs(4)
Both DZFL/R pin
SYNC Operation (1)
Internal Counter
Reset
Internal
Data
2~3/fs (2)
Figure 61. Synchronizing Sequence by RSTN Bit
Notes:
(1) The DZFL and the DZFR pins become “H” by a falling edge of RSTN bit, and becomes “L” 2/fs after a
rising edge of internal signal of RSTN bit. The synchronize function is valid During the DZFL/R pin =
“H”.
(2) Internal data is fixed to “0” forcibly for 2 to 3/fs when the internal counter is reset.
(3) Since the analog output corresponding to digital input has group delay (GD), it is recommended to
have a no-input period longer than the group delay before writing “0” to RSTN bit.
(4) It takes 3 to 4/fs when falling to change the internal RSTN signal of the LSI after writing to RSTN bit. It
also takes 2 to 3/fs when rising to change the internal RSTN signal of the LSI. The synchronize
function becomes valid immediately when “0” is written to RSTN bit. Therefore, there is a case that the
internal counter is reset before internal RSTN signal of the LSI is changed.
(5) A click noise occurs on the rising or falling edge of the internal RSTN signal and when the internal
counter is reset. This noise is output even if a “0” data is input. Mute the analog output externally if this
click noise affects the system performance.
016011073-E-00
2016/12
- 78 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
