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AK4492ECB 参数 Datasheet PDF下载

AK4492ECB图片预览
型号: AK4492ECB
PDF下载: 下载PDF文件 查看货源
内容描述: [Quality Oriented 32-Bit 2ch DAC]
分类和应用:
文件页数/大小: 101 页 / 2100 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4492]  
Synchronize Function (PCM Mode, EXDF Mode)  
The AK4492 has a function that resets the internal counter to keep the timing of falling edge of the internal  
clock CLK1 and the external clock edge in a certain range. With this synchronize function, group delays  
between each device can be kept within 4/256fs when using multiple AK4492s.  
Clock synchronize function becomes valid when input data of both L and R channels are 0for 8192  
times continuously in PCM mode or EXDF mode, when both L and R channels become 0and kept for  
8192 times continuously by attenuation or when RSTN bit = 0. In PCM mode, the internal counter is  
synchronized with a rising edged of LRCK (falling edge of LRCK in I2C mode), and it is synchronized with  
a rising edge of WCK in EXDF mode. In this case, the analog output has the same voltage as VCML/R.  
This function is disabled by setting SYNCE bit = 0in register control mode. Figure 60 shows a  
synchronizing sequence when the input data is 0for 8192 times continuously. Figure 61 shows a  
synchronizing sequence by RSTN bit.  
D/A In  
(Digital)  
SMUTE  
(1)  
(1)  
ATT_Level  
Attenuation  
-  
GD  
GD  
GD  
(4)  
AOUT  
(2)  
8192/fs  
(2)  
8192/fs  
Both DZFL/R pin  
SYNC  
SYNC  
Operation (2)  
Operation (2)  
Internal Counter  
Reset  
(5)  
Internal  
Data  
2~3/fs (3)  
Figure 60. Synchronizing Sequenc by Continuous 0Data Input for 8192 Times  
Notes:  
(1) Regarding ATT Transition time, refer to Output Volume (PCM Mode, DSD Mode, EXDF Mode).  
(2) When both L and R channels data are 0for 8192 times continuously, the DZFL and DZFR pins  
become Hand the synchronize function is valid.  
(3) Internal data is fixed to 0forcibly for 2 to 3/fs when internal counter is reset.  
(4) A click noise may occur when the internal counter is reset. This noise is output even if a 0data is  
input. Mute the analog output externally if this click noise affects the system performance.  
(5) When the internal clock and external clock are in synchronization, the internal counter is not reset  
even if the synchronize function is valid.  
016011073-E-00  
2016/12  
- 77 -  
 
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