[AK4492]
[2] Power ON/OFF by PW bit
All circuits including control register and IREF (except LDO when the LDOE pin = “H”) stop operation by
setting PW bit to “0”. In this case, control register access is available. The analog output goes to floating
state (Hi-Z). Figure 58 shows power ON/OFF sequence by PW bit.
PW bit
RSTN bit
(5)
(5)
(3)
Internal
State
Power-off
Normal Operation
Normal Operation
DAC In
(Digital)
“0” data
GD
GD
(1)
(1)
(2) Hi-Z
DAC Out
(Analog)
(3)
DZFL/DZFR
(4)
External
MUTE
(6)
Mute ON
Figure 58. Power ON/OFF Timing Example
Notes:
(1) The analog output corresponding to the digital input has group delay (GD).
(2) The analog output is floating (Hi-Z) state when PW bit = “0”.
(3) Click noise occurs at the edge of PW bit. This noise is output even if “0” data is input.
(4) The zero detect function is enable when the AK4492 is power off (PW bit= “0”). This figure shows
the seuqnece when DZFE bit= “1”, DZFB bit = “0” and DZFM bit= “0”.
(5) It takes 4~5/fs until a power down instruction is valid when writing PW bit and it takes 1~2/fs when
releasing the power down.
(6) Mute the analog output externally if click noise (3) or Hi-z output (2) adversely affect system
performance.
016011073-E-00
2016/12
- 75 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
