[AK4492]
[3] Reset by RSTN bit
Digital circuits except control registers and clock divider are reset by setting RSTN bit to “0”. In this case,
control register settings are held, the analog output becomes VCML/R voltage and the DZFL/R pin
outputs “H”. Figure 59 shows power ON/OFF sequence by RSTN bit.
RSTN bit
3~4/fs (5)
2~3/fs (5)
Internal
RSTN signal
Internal
State
Digital Block Power-off
Normal Operation
Normal Operation
DAC In
(Digital)
“0” data
GD
GD
(1)
(1)
(3)
(2)
(3)
DAC Out
(Analog)
2/fs(4)
DZFL/R
(6)
Figure 59. Reset Timing Example
Notes：
(1) The analog output corresponding to the digital input has group delay (GD).
(2) The analog output is VCOM voltage when RSTN bit = “0”.
(3) Click noise occurs at the edge of PW bit. This noise is output even if “0” data is input.
(4) This figure shows the seuqnece when DZFE bit= “1”, DZFB bit = “0” and DZFM bit= “0”. The
DZFL/R pin goes “H” on a falling edge of RSTN bit and goes “L” 2/fs after a rising edge of internal
RSTN bit.
(5) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes
2~3/fs when changing RSTN bit to “1”.
(6) Mute the analog output externally if click noise (3) adversely affect system performance.
016011073-E-00
2016/12
- 76 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
