[AK4492]
The system timing example of power up/down when not using LDO (LODE pin = “L”) is shown in Figure
56. When the LDOE pin= “L”, 1.8V (DVDD), 3.3V (AVDD, TVDD) and 5V (VDDL, VDDR) power supplies
should be powered up at the same time, otherwise power up the 3.3V power supplies (AVDD, TVDD) first,
1.8V power supply (DVDD) next and 5V power supplies (VDDL/R) last.
Power
(TVDD,AVDD)
Power
(DVDD)
Power
(VDDL/R)
Analog Reference
(VREFHL/R)
(2)
PDN pin
Internal PDN
RSTN bit
(3)
(9)
Internal State
(Resister
(Clock devider)
Power Off
Normal Operation
Normal Operation
Power Off
(10)
(10)
Internal State
(Digital Core)
Power Off
Power Off
DAC In
(Digital)
“0”data
“0”data
(4)
GD
GD
(5)
(1)
(6)
(6)
(5)
(1)
DAC Out
(Analog)
Clock In
MCLK,LRCK,BICK
(11)
Don’t Care
(8)
DZFL/R
External
Mute
(7)
Mute ON
Mute ON
Figure 56. Power-down/up Sequence Example (Resister Control Mode, LDOE pin = “L”)
Notes:
(1) Do not input a clock when power supplies are powered down.
(2) The PDN pin must be held “L” for more than 150ns after AVDD, TVDD and VDDL/R reached
90%.
(3) Internal shutdown switch is powered up after the PDN pin = “H” when the LDOE pin= “L”. The
internal circuit will start operation after the shutdown switch is ON (max. 1us).
(4) The analog output corresponding to the digital input has group delay (GD).
(5) Analog outputs are floating (Hi-Z) in power down mode.
(6) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(7) Mute the analog output externally if click noise (6) adversely affect system performance.
(8) The DZFL/R pin is “L” in power-down mode (PDN pin = “L”).
(9) The clock divider is powered up in about 4/fs after the internal PDN is released.
(10) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes
2~3/fs when changing RSTN bit to “1”.
(11) Clock inputs (MCLK, BICK and LRCK) can be stopped in power down state.
016011073-E-00
2016/12
- 73 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
