[AK4492]
■ Power Up/Down Function
The AK4492 is powered down by setting the PDN pin to “L”. In power-down state, all circuits stop
operation and initialized, and the analog output becomes floating (Hi-z) state. The PDN pin must held “L”
for more than 150ns for a certain reset. There is a possibility of malfunctions with the “L” pulse less than
150ns. Power-down is released by setting the PDN pin to “H” from “L”. In this time IREF and LDO (if
LDOE pin = “H”) are powered up and the analog output becomes floating (Hi-z) state. The Analog
common voltage power up after by PDN pin to “H”. The time to be stable voltage is in propotional to the
capacitance of the VCML pin and the VCMR pin. For example, when the capacitance is 1uF, the time
constant is about 3ms.
(1) Pin Control Mode (PSN pin = “H”)
All circuits will be powered up by inputting MCLK, LRCK and BICK clocks after the PDN pin = “H”. The
analog circuit starts operation just after supplying all necessary clocks (MCLK, LRCK and BICK) and the
digital circuit starts operation about 4/fs after the clock supply. Figure 53 shows system timing example of
power down/up when using the internal LDO (LDOE pin “H”). When power up the AK4492 with the LDOE
pin = “H”, 3.3V power supplies (AVDD and TVDD) should be powered up before or at the same time of 5V
power supplies (VDDL/R).
Power
(TVDD,AVDD)
Power
(VDDL/R)
Analog Reference
(VREFHL,VREFHR)
PDN pin
(2)
DVDD pin
(3)
Internal PDN
Internal State
Normal Operation (DAC Input Available)
Reset
DAC In
(Digital)
“0”data
“0”data
(4)
GD
GD
(5)
(6)
(6)
(8)
(5)
(1)
DAC Out
(Analog)
Clock In
MCLK,LRCK,BICK
(1)
Don’t care
External
Mute
(7)
Mute ON
Mute ON
Figure 53. Power-down/up Sequence Example (PinControl Mode, LDOE pin = “H”)
Notes:
(1) Do not input a clock when power supplies are powered down.
(2) The PDN pin must be held “L” for more than 150ns after AVDD, TVDD and VDDL/R reached
90%.
(3) Internal LDO is powered up after the PDN pin = “H” when the LDOE pin= “H”. The internal circuit
will starts operation after the shutdown switch is ON (max. 2ms) following the internal oscillator
count up.
(4) The analog output corresponding to the digital input has group delay (GD).
(5) Analog outputs are floating (Hi-Z) in power down mode.
(6) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
016011073-E-00
2016/12
- 70 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
