[AK4492]
Parameter
Symbol
Min. Typ. Max. Unit
Control Interface Timing (3-wire IF mode):
CCLK Period
200
80
80
40
40
150
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
CCLK Pulse Width Low
CCLK Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “” to CCLK “”
tCSH
CCLK “” to CSN “”
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
kHz
usec
usec
usec
usec
usec
usec
usec
usec
usec
usec
nsec
pF
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
(Note 44) tHD:DAT
tSU:DAT
tR
tF
tSU:STO
0.6
0
-
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
tSP
Cb
Power-down & Reset Timing
PDN Accept Pulse Width
PDN Reject Pulse Width
(Note 45)
tAPD
tRPD
150
-
-
-
-
30
nsec
nsec
Note 44. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 45. The AK4492 should be reset by bringing the PDN pin “L” upon power-up.
Note 46. I2C -bus is a trademark of NXP B.V.
016011073-E-00
2016/12
- 30 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
