[AK4492]
(Ta = -40 ~ 85 C; VDDL/R = 4.755.25 V, TVDD = AVDD = (DVDD) 3.6V, DVDD = 1.7~1.98 V,
CL = 20 pF, PSN pin = “L”, AFSD bit = “1”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing (FS Auto Detect Mode)
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
7.68
40
9.155
9.155
-
-
-
-
MHz
%
nsec
nsec
49.152
60
-
-
LRCK Clock Timing (FS Auto Detect Mode) (Note 38)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
Duty Cycle
fsn
fsd
fsq
fso
fsh
30
88.2
176.4
-
-
45
-
-
-
54
108
216
-
-
55
kHz
kHz
kHz
kHz
kHz
%
384
768
-
Duty
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
fsn
fsd
fsq
tLRH
tLRL
30
88.2
176.4
1/128fs
1/128fs
-
-
-
-
-
54
108
216
-
kHz
kHz
kHz
nsec
nsec
Low time
-
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
fsn
fsd
tLRH
tLRL
30
-
1/256fs
1/256fs
-
-
-
-
54
108
-
-
kHz
kHz
nsec
nsec
Low time
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
High time
fsn
tLRH
tLRL
30
1/512fs
1/512fs
-
-
-
54
-
-
kHz
nsec
nsec
Low time
Note 38. Normal operation is not guaranteed if a frequency not shown above is input to the LRCK when
the AK4492 is in Sampling Frequency Auto Detect Mode.
016011073-E-00
2016/12
- 27 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
